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ZY8160 60A DC-DC Intelligent POL
8V to 14V Input ? 0.5V to 2.75V Output
Data Sheet
Figure 40 shows the input voltage noise of the three-
output system with programmed interleave. Instead
of all three POLs switching at the same time as in
the previous example, the POLs V1, V2, and V3
switch at 67.5°, 180°, and 303.75°, respectively.
Noise is spread evenly across the switching cycle
resulting in more than 1.5 times reduction. To
achieve similar noise reduction without the interleave
will require the addition of an external LC filter.
Figure 42. Output Voltage Noise, Full Load, 180 ? Interleave
ZY8160 interleave is independent of the number of
POLs in a system and is fully programmable in
11.25 ? steps. It allows maximum output noise
reduction by intelligently spreading switching energy.
Note : Due to noise sensitivity issues that may occur in limited
cases, it is recommended to avoid phase lag settings of
112.5 and 123.75 degrees, otherwise false PG and/or OV
indications may occur.
Figure 40. Input Voltage Noise with Interleave
DC ?
,
Similar noise reduction can be achieved on the
output of POLs connected in parallel. Figure 41 and
Figure 42 show the output noise of two POLs
connected in parallel without and with a 180°
interleave, respectively. Resulting noise reduction is
more than 2 times and is equivalent to doubling
switching frequency or adding extra capacitance on
the output of the POLs.
8.4.3 Duty Cycle Limit
The ZY8160 is a step-down converter therefore V OUT
is always less than V IN . The relationship between
the two parameters is characterized by the duty
cycle and can be estimated from the following
equation:
V OUT
V IN . MIN
Where, DC is the duty cycle, V OUT is the required
maximum output voltage (including margining),
V IN.MIN is the minimum input voltage.
It is good practice to limit the maximum duty cycle of
the PWM controller to a somewhat higher value
compared to the steady-state duty cycle as
expressed by the above equation. This will further
protect the output from excessive voltages. The duty
cycle limit can be programmed in the GUI PWM
Controller window or directly via the I 2 C bus by
writing into the DCL register shown in Figure 43.
Figure 41. Output Voltage Noise, Full Load, No Interleave
ZD-01674 Rev. 1.2, 02-Jul-10
www.power-one.com
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